1. Field of the Invention
The present invention relates to a system in package (SIP) semiconductor device, and a method of managing the power of the SIP semiconductor device, and more particularly, to an SIP semiconductor device that can be effectively power-managed, and a method of managing the power of the SIP semiconductor device.
2. Description of the Related Art
FIG. 1 illustrates a conventional system in package (SIP) semiconductor device 100.
Referring to FIG. 1, the conventional SIP semiconductor device 100 includes two or more chips that are packed in one semiconductor device.
For example, in the conventional SIP semiconductor device 100, a first chip 130 formed on a lower level may include memory interfaces 103 and a controller 105, and a second chip 110 formed on a higher level may include a memory as a storage unit. Hence, the second chip 110 stores data, and the first chip 130 controls the operation of the second chip 110.
The first chip 130 reads/writes data from/to the second chip 110 using the memory interfaces 103. In addition, the first chip 130 controls power-down and wake-up operations of the conventional SIP semiconductor device 100 including the second chip 110 by using the controller 105.
In the power-down mode, power is not supplied to the conventional SIP semiconductor device 100 except to components (e.g., a real time clock) performing essential operations of the conventional SIP semiconductor device 100. In the wake-up mode, the conventional SIP semiconductor device 100 is activated so as to operate. The terms “power-down mode” and “wake-up mode” are known to one of ordinary skill in the related art.
In the conventional SIP semiconductor device 100, the first chip 130 controls power supply to the second chip 110. Hence, the second chip 110 cannot manage the power supplied thereto. As a result, power supply management cannot be flexibly performed in the conventional SIP semiconductor device 100. Moreover, in this case, it is disadvantageous that the second chip 110 only be configured with the memory, hence, a separate interface or a controller is also included in the second chip 110.
In another conventional SIP semiconductor device, each of the first and second chips 130 and 110 includes a controller, a memory, and an interface. However, it has not been disclosed how the first and second chips are respectively power-managed and only a packaging method for connecting signal lines of the first and second chips 130 and 110 has been disclosed.
Therefore, there is a need for an effective power supply management method for an SIP semiconductor device including a plurality of chips each having a controller, a memory, and an interface. Furthermore, for size reduction and low power consumption, it is required that the SIP semiconductor device include the chips and operate by interlocking the chips. Thus, an SIP semiconductor device suitable for effective power management is required.